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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity jianjian is
port(
A : in vl_logic_vector(7 downto 0);
B : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_s_24 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_sstl3_ii_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffxi_m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdx_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hmap_puc is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fmap_puo is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2