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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20k_ram_slice is
generic(
operation_mode : string := "single_port";
deep_ram_mode : string := "off";
logical_ram_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftnld
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftn
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_transmitter is
generic(
channel_num : integer := 1;
channel_width : integer := 8;
serialization_factor:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_reset_block is
port(
txdigitalreset : in vl_logic_vector(3 downto 0);
rxdigitalreset : in vl_logic_vector(3 downt
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_receiver is
generic(
channel_num : integer := 1;
channel_width : integer := 20;
deserialization_factor:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_deskew_fifo is
generic(
a : integer := 195;
\FIFO_DEPTH\ : integer := 16
);
port(
datain
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftn