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Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_all_signals_3_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 23:49:15 Verilog_XL_Turbo_NT 2.6.9

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_all_signals_1_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 23:29:16 Verilog_XL_Turbo_NT 2.6.9

# # sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows # CDS_INST_DIR=c:/progra~1/cds SOURCES = \ show_all_nets_acc.c \ show_all_

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_all_signals2_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Jan 5, 1999 05:53:48 Verilog_XL_Turbo_NT 2.6.9

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_all_signals3_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Jan 5, 1999 06:11:49 Verilog_XL_Turbo_NT 2.6.9

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: list_pathout_ports_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Jan 6, 1999 01:23:07 Verilog_XL_Turbo_NT 2.6.9

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_value_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 19:18:32 Verilog_XL_Turbo_NT 2.6.9 Nov 24,

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: list_parameters_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 13:27:47 Verilog_XL_Turbo_NT 2.6.9 Fe

/********************************************************************** * $exprinfo_test example -- Verilog HDL test bench. * * Verilog test bench to test the $exprinfo_test PLI application. *

/********************************************************************** * $propagatep_test example -- Verilog HDL test bench. * * Verilog test bench to test the $propagatep_test PLI application.