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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: list_pathout_ports_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998 02:33:30 Verilog_XL_Turbo_NT 2.6.9

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: count_all_prims_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998 03:01:40 Verilog_XL_Turbo_NT 2.6.9 No

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: read_strengthval_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998 22:02:21 Verilog_XL_Turbo_NT 2.6.9 N

/********************************************************************** * $read_test_vector example -- Verilog test bench source code * * Verilog test bench to test the $read_test_vector PLI app

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE Command arguments: show_all_signals_2_test.v Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 23:43:51 Verilog_XL_Turbo_NT 2.6.9

# # sample NMAKE makefile to make libvpi.dll with VisualC++ on Windows # see windows.txt for more details. # SOURCES = \ show_all_nets_vpi.c \ # show_all_signals_1_vpi.c \