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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s2_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s2_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s9 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_upad is
port(
pad : inout vl_logic
);
end x_upad;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s4_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s2_s36 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb16_s1_s36 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_pu is
port(
o : out vl_logic
);
end x_pu;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_keeper is
port(
o : inout vl_logic
);
end x_keeper;