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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hmap is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_iv is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut4 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor5b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_28 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufsn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos33_s_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufs_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos18_f_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i