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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgls is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufd_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pullup is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic
);
end pullup;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufdn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity inv is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tck is
generic(
cds_action : string := "ignore"
);
port(
i : inout vl_logic
);
end tck;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_37 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in