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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufg is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_dv2_33 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pulldown is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic
);
end pulldown;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_05 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_28 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufsn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufs_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufd_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic