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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_i_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufe_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_infiniband_4 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s4_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rdbk is
generic(
cds_action : string := "ignore"
);
port(
data : out vl_logic;
rip
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tdo is
generic(
cds_action : string := "ignore"
);
port(
o : in vl_logic
);
end tdo;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :