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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2_s2 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity buffclk is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufe is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_34 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_23 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity keeper is
generic(
cds_action : string := "ignore"
);
port(
o : inout vl_logic
);
end keeper;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnsn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic