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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s36 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s2 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity orcy is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ci
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnsn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_09 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildi_1u is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_15 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1