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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_xaui_1 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_flag
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult18x18s is
port(
p : out vl_logic_vector(35 downto 0);
a : in vl_logic_vector(17 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_25 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_18 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s1 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi