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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgs is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_39 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_infiniband_1 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_42 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in