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找到约 10,000 项符合 Verilog 的代码

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobufs_f_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_log

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvdci_dv2_18 is port( o : out vl_logic; io : inout vl_logic; i : in

_primary.vhd

library verilog; use verilog.vl_types.all; entity ofd is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q : o

_primary.vhd

library verilog; use verilog.vl_types.all; entity cy4_30 is generic( cds_action : string := "ignore" ); port( c0 : out vl_logic; c1

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobufs_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_log

_primary.vhd

library verilog; use verilog.vl_types.all; entity cy4_22 is generic( cds_action : string := "ignore" ); port( c0 : out vl_logic; c1

_primary.vhd

library verilog; use verilog.vl_types.all; entity readback is generic( cds_action : string := "ignore" ); port( data : out vl_logic; rip

_primary.vhd

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos25_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in

_primary.vhd

library verilog; use verilog.vl_types.all; entity ramb4_s8_s16 is generic( cds_action : string := "ignore"; init_00 : integer := 0; init_01 : integer

_primary.vhd

library verilog; use verilog.vl_types.all; entity bufgp_f is port( o : out vl_logic; i : in vl_logic ); end bufgp_f;