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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_10 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_04 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ld is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_08 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ild_1m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtlp_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi