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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_ethernet_2 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_rep
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufgp is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_ethernet_4 is
generic(
clk_cor_insert_idle_flag: string := "FALSE";
clk_cor_keep_idle: string := "FALSE";
clk_cor_rep
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_16 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tdi is
generic(
cds_action : string := "ignore"
);
port(
i : inout vl_logic
);
end tdi;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_26 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufdn_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i