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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity buf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufge is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s4_s9 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity xorcy is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ci
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity buft is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufn is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v