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Verilog 的代码
pulse_16_sum.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
ps2tolcd.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
barrel_shifter.hif
Version 6.1 Build 201 11/27/2006 SJ Full Version
11
782
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
gray_counter.hif
Version 6.1 Build 201 11/27/2006 SJ Full Version
11
782
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity booth_mul is
port(
M : in vl_logic_vector(3 downto 0);
Q : in vl_logic_vector(3 downto 0);
lab1.hif
Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
38
2267
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
i2c.map.rpt
Analysis & Synthesis report for i2c
Sun Jul 06 20:50:47 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1
ps2tolcd.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
dds.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity keyscan is
generic(
sr : integer := 15;
s0 : integer := 14;
s1 : integer := 13;