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Verilog 的代码
verilog.h
#ifndef __VERILOG_H
#define __VERILOG_H
struct ltype
{
unsigned first_line;
unsigned first_column;
unsigned last_line;
unsigned last_column;
const char*text;
};
#define YYLTYPE ltype
extern
verilog.hh
/*
* Copyright (c) 2000-2002 moe
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License
verilog.y
%{
/*
* Copyright (c) 1999-2002 moe
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public Lice
verilog.cc
/*
* Copyright (C) 2000-2001 moe
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License
verilog.log
Host command: /shared/tools/ncsim/tools/verilog/bin/verilog.exe
Command arguments:
../../../bench/verilog/oc8051_tb.v
../../../rtl/verilog/oc8051_top.v
../../../rtl/verilog/oc8051_alu_src1
make_verilog
verilog ../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_