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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altlvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_output: string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altcam is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 1;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_8b10b_decoder is
port(
clk : in vl_logic;
reset : in vl_logic;
errdetectin : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity divide_by_two is
generic(
divide : string := "true"
);
port(
clkin : in vl_logic;
clkout
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(10 downto 0);
\A\ : in vl_logic_vector(10 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_jtagb is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);