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Verilog 的代码
ps2.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom is
port(
data : out vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(12 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
generic(
HLT : integer := 0;
SKZ : integer := 1;
ADD : integer := 2;
\A
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram is
port(
data : inout vl_logic_vector(7 downto 0);
addr : in vl_logic_vector(9 downto 0);
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity accum is
port(
accum : out vl_logic_vector(7 downto 0);
data : in vl_logic_vector(7 downto 0);
run_options.txt
#-- Synplicity, Inc.
#-- Version 9.4A1
#-- Project file D:\Actelprj\LCD_1602\synthesis\run_options.txt
#-- Written on Thu Jan 29 17:10:47 2009
#add_file options
add_file -verilog "D:/Actelprj
lcd_top_syn.prj
#add_file options
add_file -verilog "D:/Actelprj/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "D:/Actelprj/LCD_1602/hdl/Clock_Gen.v"
add_file -verilog "D:/Actelprj/LCD_1602/hdl/LCD_Driver.v
i2c_sl~2.sty
[Normal]
synlibXRef=lc4k_vlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_vlg, Verilog.TASKLSVlog, 0, True
[STRATEGY-LIST]
Normal=True, 1125078904
[TOUCHED-REPORT]
Design.bl2File=1125087229
ps2.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
plvji.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu