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library verilog; use verilog.vl_types.all; entity mf_pll_reg is port( q : out vl_logic; clk : in vl_logic; ena : in vl_logi

library verilog; use verilog.vl_types.all; entity hcstratix_ram_clear is port( aclr : in vl_logic; d : in vl_logic; clk : in

library verilog; use verilog.vl_types.all; entity stratix_ram_clear is port( aclr : in vl_logic; d : in vl_logic; clk : in

library verilog; use verilog.vl_types.all; entity io_buf_tri is port( datain : in vl_logic; dataout : out vl_logic; oe : in vl_logi

library verilog; use verilog.vl_types.all; entity b17mux21 is port( mo : out vl_logic_vector(16 downto 0); a : in vl_logic_vector(16 downto 0);

library verilog; use verilog.vl_types.all; entity hcstratix_lcell is generic( operation_mode : string := "normal"; synch_mode : string := "off"; register_cascade_mo

library verilog; use verilog.vl_types.all; entity altlvds_rx is generic( number_of_channels: integer := 1; deserialization_factor: integer := 4; registered_output: string

library verilog; use verilog.vl_types.all; entity altcam is generic( width : integer := 1; widthad : integer := 1; numwords : integer := 1;

library verilog; use verilog.vl_types.all; entity mux41 is port( mo : out vl_logic; in0 : in vl_logic; in1 : in vl_logic;

library verilog; use verilog.vl_types.all; entity glbl is generic( ROC_WIDTH : integer := 100000; TOC_WIDTH : integer := 0 ); end glbl;