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# ****************************************************************************** # ****************************************************************************** # This makefile contains the rules for

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

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Version 7.0 Build 33 02/05/2007 SJ Full Version 35 1941 OFF OFF OFF OFF ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- --

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

verilog ../../../syn/src/verilog/oc8051_fpga_top.v ../../../bench/verilog/oc8051_fpga_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_

library verilog; use verilog.vl_types.all; entity dpram8x32 is port( data : in vl_logic_vector(7 downto 0); wren : in vl_logic; wraddress

library verilog; use verilog.vl_types.all; entity stratix_lcell is generic( operation_mode : string := "normal"; synch_mode : string := "off"; register_cascade_mode

library verilog; use verilog.vl_types.all; entity bmux21 is port( mo : out vl_logic_vector(15 downto 0); a : in vl_logic_vector(15 downto 0);