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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pingpang is
port(
clk_5m : in vl_logic;
rst : in vl_logic;
nd : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
dk74x191.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity test_I2C_to_GPIO is
generic(
tdelay : real := 3.500000;
testcycle : real := 100.000000
);
end test_I2C_to
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
mo : out vl_logic_vector(15 downto 0);
a : in vl_logic_vector(15 downto 0);