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Verilog 的代码
ohmacro.txt
verilog
oh.rc
@vericom rc file Version 1.0
[oh]
invokeDir = /ae9b/hlhsiao/testcase/demo43/verilog/rtl_mt_libs
hostCommand = -f run_veri_test.f
run.f
../../design_src/verilog/gate/system.v
../../design_src/verilog/src/pram.v
-v ../../design_src/verilog/src/mem.v
../../design_src/verilog/gate/CPU.vg
verilog.dump
$date
Aug 14, 1997 17:28:33
$end
$version
VERILOG-XL 2.5
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var paramete
verilog.dump
$date
Jul 26, 1997 13:37:48
$end
$version
VERILOG-XL 2.3.3
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var parame
at_xst.prj
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/synth_defs.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at
repository
ethernet/bench/verilog
repository
ethernet/rtl/verilog
repository
wb_dma/bench/verilog
entries
D/verilog////