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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufge_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_s_2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_f_8 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_hstl_ii_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s4 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x4s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvdci_dv2_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1d_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
dpo