代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/198746/6786438
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mvbc3tbw is
end mvbc3tbw;
www.eeworm.com/read/473809/6841718
qsf fpga_pro.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/294637/8214585
zsf wed.zsf
E:/电子设计竞赛/verilog/62256接口/db/62256.sim.vwf 0 1250000 445 1250000 0
E:/电子设计竞赛/verilog/62256接口/62256.vwf 0 2500000 612 2500000 0
E:/电子设计竞赛/verilog/62256接口/Waveform1.vwf 0 1000000 799 1000000 4
62256.
www.eeworm.com/read/173063/9676458
qsf cfb_sp.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/172784/9690184
v vpi_utilities_test.v
/**********************************************************************
* $vpi_util_test example -- Verilog HDL test bench.
*
* Verilog test bench to test the VPI utility applications.
*
*
www.eeworm.com/read/172784/9690216
v list_pathout_ports_test.v
/**********************************************************************
* $list_pathout_ports example -- Verilog HDL test bench.
*
* Verilog test bench to test the $list_pathout_ports PLI applic
www.eeworm.com/read/172784/9690230
v vpi_utilities_test.v
/**********************************************************************
* $vpi_util_test example -- Verilog HDL test bench.
*
* Verilog test bench to test the VPI utility applications.
*
*
www.eeworm.com/read/172784/9690232
v show_all_nets_test.v
/**********************************************************************
* $show_all_nets example -- Verilog HDL test bench.
*
* Verilog test bench to test the $show_all_nets PLI application on a
www.eeworm.com/read/172784/9690237
log realpow_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
realpow_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 27, 1998 19:52:24
Verilog_XL_Turbo_NT 2.6.9 Nov 27, 19
www.eeworm.com/read/172784/9690247
log read_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 28, 1998 00:53:09
Verilog_XL_Turbo_NT 2.6.9 Nov 28