代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585938
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or5b4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585942
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom256x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585950
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ram32 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i : i
www.eeworm.com/read/159314/5585951
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_latche is
port(
o : out vl_logic;
i : in vl_logic;
clk : in vl_logic;
www.eeworm.com/read/159314/5585960
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor32 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5585965
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ff is
port(
o : out vl_logic;
i : in vl_logic;
clk : in vl_logic;
www.eeworm.com/read/159314/5585966
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_fdd is
port(
o : out vl_logic;
i : in vl_logic;
clk : in vl_logic;
www.eeworm.com/read/159314/5585977
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_latch is
port(
o : out vl_logic;
i : in vl_logic;
clk : in vl_logic;
www.eeworm.com/read/159314/5585981
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams64 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5585982
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams32 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :