代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585887
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldp_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585895
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585900
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585904
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf5_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
www.eeworm.com/read/159314/5585914
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf7_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
www.eeworm.com/read/159314/5585915
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585922
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585926
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom64x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585928
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode4 is
port(
o : out vl_logic;
a0 : in vl_logic;
a1 : in vl_logic;
www.eeworm.com/read/159314/5585934
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_33 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_