代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585763
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585775
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf5_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
www.eeworm.com/read/159314/5585777
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585785
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtxi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
www.eeworm.com/read/159314/5585786
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf6_d is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
lo
www.eeworm.com/read/159314/5585794
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585796
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdrs_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585797
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585798
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut3 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
www.eeworm.com/read/159314/5585799
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fds_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :