代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585735
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildxi_1f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585737
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srlc16e_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585740
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldcp is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585743
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or5b3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585748
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4b4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585749
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585753
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdc_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585755
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtlp is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585761
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585762
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildx_1f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q