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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos18_f_8 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufns_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_i_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufe_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fds is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q : o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_s_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilffxi_f is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_infiniband_4 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idl