代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585387
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxcy is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ci
www.eeworm.com/read/159314/5585390
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdp_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585392
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585406
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585409
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585413
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585414
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
www.eeworm.com/read/159314/5585420
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585422
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585423
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o