代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585232
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldc_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585235
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x2s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
www.eeworm.com/read/159314/5585236
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_25 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585238
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
www.eeworm.com/read/159314/5585240
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585241
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtxi_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585244
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdse_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585258
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585259
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvdci_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_
www.eeworm.com/read/159314/5585261
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in