代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585089
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srlc16_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585092
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585100
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf8_l is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
www.eeworm.com/read/159314/5585101
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585117
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585120
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtl is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585121
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode8 is
port(
o : out vl_logic;
a0 : in vl_logic;
a1 : in vl_logic;
www.eeworm.com/read/159314/5585125
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdcpe_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585127
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflxi_1m is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5585128
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdpe is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :