代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585028
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildx_1u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585032
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585041
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585042
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585047
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x2s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
www.eeworm.com/read/159314/5585062
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdp is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q : o
www.eeworm.com/read/159314/5585063
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram64x1s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585079
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom128x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585086
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585088
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x1s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o