代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584871
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_s_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584872
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fmap is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
www.eeworm.com/read/159314/5584881
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584884
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5584893
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5584898
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_s_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584899
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos18_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5584904
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s16_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer
www.eeworm.com/read/159314/5584912
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdre_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584913
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdr is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : o