代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5584827
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pci33_5 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
www.eeworm.com/read/159314/5584832
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16e is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584834
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584836
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity srl16e_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584843
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf7 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5584845
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdrse_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584853
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_agp is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5584856
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5584860
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram128x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5584867
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdxi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :