代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/207756/15262701
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sub2 is
generic(
w2 : integer := 17
);
port(
dataa : in vl_logic_vector;
datab
www.eeworm.com/read/207756/15262704
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sub1 is
generic(
w1 : integer := 9
);
port(
dataa : in vl_logic_vector;
datab
www.eeworm.com/read/207756/15262707
cmd_log test.cmd_log
sch2verilog -intstyle ise -family spartan3 -w "D:/xilinx/lianxi/diexingbianhuan/test.sch" test.vf
www.eeworm.com/read/207756/15262800
cmd_log lian.cmd_log
sch2verilog -intstyle ise -family spartan3 -w "D:/xilinx/lianxi/diexingbianhuan/lian.sch" lian.vf
sch2verilog -intstyle ise -family spartan3 -w "D:/xilinx/lianxi/diexingbianhuan/lian.sch" lian.vf
www.eeworm.com/read/206514/15294023
_prj iq_pn_gen._prj
insert `timescale 1ns/1ns
include
include iq_pn_gen.v
include D:/Xilinx/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/206514/15294039
crp coregen.crp
NEWPROJECT j:\projects\ise\arch_wzd_demo
SETPROJECT j:\projects\ise\arch_wzd_demo
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Virtex2P
SET FlowVendor = Foundation_iSE
SET DesignFlow
www.eeworm.com/read/168634/5441248
rc oh.rc
@vericom rc file Version 1.0
[oh]
invokeDir = /ae9b/hlhsiao/testcase/demo43/verilog/rtl_mt_libs
hostCommand = -f run_work.f
www.eeworm.com/read/159314/5584768
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldpe_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
www.eeworm.com/read/159314/5584776
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdce_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5584780
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_8 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in