代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11691101
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_t02 is
port(
t02_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691126
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_l31 is
port(
l31_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691163
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_l04 is
port(
l04_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691169
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux4 is
port(
\Y\ : out vl_logic;
\I0\ : in vl_logic;
\I1\ : in vl_logic;
www.eeworm.com/read/347114/11691183
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_t11 is
port(
t11_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691189
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_t20 is
port(
t20_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691210
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_l40 is
port(
l40_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691254
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and11 is
port(
\Y\ : out vl_logic_vector(10 downto 0);
\IN1\ : in vl_logic_vector(10 downto 0)
);
www.eeworm.com/read/347114/11691260
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
I9clNoF=RU4[`QRa?cQ?YI3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/flex10ke_atoms.v)
L0 1144
OV;L
www.eeworm.com/read/347114/11691268
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;