代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/172784/9690419
log hello_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
hello_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 11:22:44
Verilog_XL_Turbo_NT 2.6.9 Nov 24, 1998
www.eeworm.com/read/172784/9690421
v show_value_test.v
/**********************************************************************
* $show_value example -- Verilog HDL test bench.
*
* Verilog test bench to test the $show_value PLI application on a
*
www.eeworm.com/read/172784/9690435
log my_monitor1_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_monitor1_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 26, 1998 03:15:05
Verilog_XL_Turbo_NT 2.6.9 Dec 26
www.eeworm.com/read/172784/9690470
log my_monitor2_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_monitor2_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Feb 10, 1999 13:16:34
Verilog_XL_Turbo_NT 2.6.9 Feb 10
www.eeworm.com/read/172784/9690476
v list_nets_test.v
/**********************************************************************
* $list_nets example -- Verilog test bench source code
*
* Verilog test bench to test the $list_nets PLI application.
*
www.eeworm.com/read/172784/9690576
v sci_alu_sequential_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690589
v sci_alu_combinational_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690605
v read_4state_value_test.v
/**********************************************************************
* $read_4state_value example -- Verilog HDL test bench.
*
* Verilog test bench to test the $read_4state_value PLI applicat
www.eeworm.com/read/172784/9690609
v nodeinfo_test.v
/**********************************************************************
* $nodeinfo_test example -- Verilog HDL test bench.
*
* Verilog test bench to test the $nodeinfo_test PLI application.
*
www.eeworm.com/read/172784/9690614
log realpow_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
realpow_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 25, 1998 21:05:09
Verilog_XL_Turbo_NT 2.6.9 Dec 25, 19