代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
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vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
generic(
period : integer := 200;
duty_cycle : real := 0.500000;
offset : integer := 0
www.eeworm.com/read/478173/6720928
v v_hier_subprim.v
// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2009 by Wilson Snyder.
// surefire lint
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t 50_vrename.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2000-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
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t 30_preproc.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2000-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
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t 12_splitbus.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2000-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
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t 56_editfiles.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2007-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
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t 60_vpassert.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2000-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
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out 80_vppreproc_cmped.out
`line 1 "verilog/inc2.v" 1
At file `__FILE__ line `__LINE__
`line 5 "verilog/inc2.v" 0
`line 1 "verilog/inc3.v" 1
`line 2 "inc3_a_filename_from_line_directive" 0
At file `__FILE
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t 34_parser.t
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2000-2009 by Wilson Snyder. This program is free software;
# you can redistribute it and/or modify
www.eeworm.com/read/478173/6721001
out 30_preproc.out
verilog/inc2.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc2.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc2.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example sourc