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Verilog 的代码
repository
wb_conbus/rtl/verilog
compilefordebussy
#!/bin/csh -f
if(-e work.lib++) then
\rm -rf work.lib++
endif
# /dq2/qa/Debussy/prod/4.4/Main/bin/vericom \
vericom \
-v ../verilog/src/mem.v \
../verilog/RTL/TopModule.v \
../verilog/RTL/ALUB.v
compileformti
#!/bin/csh -f
if (-e work) then
\rm -rf work
endif
vlib work
vlog \
-v ../verilog/src/mem.v \
../verilog/RTL/TopModule.v \
../verilog/RTL/ALUB.v \
../verilog/RTL/CCU.v \
../verilog/FSM/master.v
verilog.dump
$date
May 4, 2000 18:30:43
$end
$version
VERILOG-XL 3.0.p001
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var par
verilog.dump
$date
Aug 14, 1997 17:28:33
$end
$version
VERILOG-XL 2.5
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var paramete
run.f
+dump+strength
../design_src/verilog/src/system.v
../design_src/verilog/src/pram.v
-v ../design_src/verilog/src/mem.v
../design_src/verilog/rtl/TopModule.v
../design_src/verilog/rtl/ALUB.v
../design_s
run_rtl.f.old
+dump+strength
../../design_src/verilog/src/system.v
../../design_src/verilog/src/pram.v
-v ../../design_src/verilog/src/mem.v
../../design_src/verilog/rtl/TopModule.v
../../design_src/verilog/rtl/ALU
run_rtl.f
+dump+strength
../design_src/verilog/src/system.v
../design_src/verilog/src/pram.v
-v ../design_src/verilog/src/mem.v
../design_src/verilog/rtl/TopModule.v
../design_src/verilog/rtl/ALUB.v
../design_s
ohmacro.txt
verilog
verilog
oh.rc
@vericom rc file Version 1.0
[oh]
invokeDir = /ae9b/hlhsiao/testcase/demo43/verilog/rtl_mt_libs
hostCommand = -f run_work.f