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library verilog; use verilog.vl_types.all; entity obuft_lvcmos15_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity fd_1 is generic( cds_action : string := "ignore"; init : integer := 0 ); port( q :

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos33_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity ibuf_hstl_iv_18 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobuf_hstl_ii_dci is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity iobufnn_f_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_lo

library verilog; use verilog.vl_types.all; entity iobuf_lvdci_18 is port( o : out vl_logic; io : inout vl_logic; i : in vl_

library verilog; use verilog.vl_types.all; entity obuft_lvttl_s_4 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos15_s_8 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity bufgmux is port( o : out vl_logic; i0 : in vl_logic; i1 : in vl_logic;