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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_4 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nor5b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut1 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut4_d is
generic(
init : integer := 0
);
port(
lo : out vl_logic;
o : ou
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_sstl3_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s2_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldc_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :