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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufds_blvds_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
io
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s1 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofd_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_iii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufds_lvds_33 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ob
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand2b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl2_ii is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_i_dci_18 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ldce_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_lvdci_25 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i