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library verilog; use verilog.vl_types.all; entity bufgs_f is port( o : out vl_logic; i : in vl_logic ); end bufgs_f;

library verilog; use verilog.vl_types.all; entity decode1_io is port( o : out vl_logic; i : in vl_logic ); end decode1_io;

library verilog; use verilog.vl_types.all; entity ram128x1s is generic( cds_action : string := "ignore"; init : integer := 0 ); port( o

library verilog; use verilog.vl_types.all; entity ramb16_s1_s1 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : integer

library verilog; use verilog.vl_types.all; entity ramb16_s1 is generic( cds_action : string := "ignore"; init : integer := 0; srval : integer :=

library verilog; use verilog.vl_types.all; entity cy4_41 is generic( cds_action : string := "ignore" ); port( c0 : out vl_logic; c1

library verilog; use verilog.vl_types.all; entity iobuf_s_12 is port( o : out vl_logic; io : inout vl_logic; i : in vl_logi

library verilog; use verilog.vl_types.all; entity iobuf_lvcmos15_f_12 is port( o : out vl_logic; io : inout vl_logic; i : in

library verilog; use verilog.vl_types.all; entity obufs_s is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_lvcmos33_s_16 is generic( cds_action : string := "ignore" ); port( o : out vl_logic;