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library verilog; use verilog.vl_types.all; entity obuf_lvttl_f_12 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity ramb16_s4_s36 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : integer

library verilog; use verilog.vl_types.all; entity obuftn_f is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_sstl2_i_dci is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuf_lvcmos15_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity obuft_sstl3_ii is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobufd_s_24 is port( o : out vl_logic; io : inout vl_logic; i : in vl_log

library verilog; use verilog.vl_types.all; entity obuf_s_6 is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i

library verilog; use verilog.vl_types.all; entity iobufd is port( o : out vl_logic; io : inout vl_logic; i : in vl_logic

library verilog; use verilog.vl_types.all; entity ibuf_gtl_dci is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i