代码搜索结果
找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity s_flag is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end s_flag;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_f_12 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdtx_f_24 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_xaui_2 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_flag
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos25_s_2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s4_s8 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_lvdci_dv2_33 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i