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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos15_f_4 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dcm is
generic(
clk_feedback : string := "1X";
clkdv_divide : real := 2.000000;
clkfx_divide : integer := 1;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut4_l is
generic(
init : integer := 0
);
port(
lo : out vl_logic;
i0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut4_l_mux4 is
end lut4_l_mux4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufdn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_39 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand4b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0